SGM48524A.pdf? Two Independent Gate Drive Channels
? 4.5V to 18V Single Supply Range (VDD)
? 5A Peak Source/Sink Pulse Current Drive
? Independent Enable Pin for Each Channel
? TTL and CMOS Compatible Logic Threshold
? Logic Levels Independent of Supply Voltage
? Hysteretic Input Logic for High Noise Immunity
? Outputs are Logic Low when Inputs are Floating
? Negative Voltage Handling Capability:
-8V DC at Inputs
-2V, 200ns Pulse for Outputs (OUTx)
? Glitch-Free Operation at Power-Up and Power-
? Down: Outputs Pulled Low during Supply UVLO
? Fast Propagation Delays: 18ns (TYP)
? Fast Rise Time: 8ns (TYP)
? Fast Fall Time: 8ns (TYP)
? Delay Matching between Two Channels: 1ns (TYP)
? Channels can be Paralleled for Higher Drive Current
-40℃ to +140℃ Operating Temperature Range
? Packaging:
SGM48523/4A/5 Available in Green SOIC-8,
MSOP-8 (Exposed Pad) and TDFN-3×3-8L Packages
SGM48526 Available in a Green TDFN-3×3-8L Package
? 工業(yè)標(biāo)準(zhǔn)引腳分配
? 兩個獨立的柵極驅(qū)動通道
? 5A峰值驅(qū)動源電流和灌電流
? 針對每個輸出的獨立使能功能
? 與電源電壓無關(guān)的TTL和CMOS兼容邏輯閥值針對高抗擾度的滯后邏輯閥值
? 輸入和使能引腳電壓電平不受VDD引腳偏置電源電壓限制
? 4.5V至18V單電源范圍
? 在VDD欠壓閉鎖(UVLO)期間，輸出保持低電平,(以確保加電和斷電時的無毛刺脈沖運行)
? 快速傳播延遲( 典型值13ns)
? 快速上升和下降時間( 典型值7ns和6ns)
? 兩通道間典型值為1ns的延遲匹配時間
? 針對更高的驅(qū)動電流，兩個輸出可以并聯(lián)
? 當(dāng)輸入懸空時輸出保持在低電平
? 環(huán)氧樹脂雙列直插式(PDIP)-8，小外形尺寸集成電路(SOIC)-8，表面貼裝小外形尺寸(MSOP)-8封裝 PowerPADTM和3mm x 3mm超薄型小外形尺寸(WSON)-8封裝選項
? -40°C 至+140°C的運行溫度范圍
